1. Field of the Invention
The present invention relates to LDMOS transistor arrays and, more particularly, to a method of monitoring mask misalignment biases of key LDMOS process steps. By characterizing these offsets, process biases can be eliminated, leading to improved electrical and hot carrier reliability performance of LDMOS arrays.
2. Description of the Related Art
A lateral DMOS (LDMOS) transistor array is a well known semiconductor structure that is commonly used in high power applications. FIGS. 1A-1B show views that illustrate a prior-art, dual-device LDMOS transistor array 100. FIG. 1A shows a plan view, while FIG. 1B shows a cross-sectional view taken along lines 1B-1B of FIG. 1A.
As shown in FIGS. 1A and 1B, array 100 includes a p− semiconductor material 110, such as an epitaxial layer or a substrate, and spaced-apart first and second n+ source strips 112 and 114 that are formed in material 110. Further, array 100 includes an n− drain extension region 116, such as a well, that is formed in p− semiconductor material 110 between source strips 112 and 114, and an n+drain strip 118 that is formed in n− drain extension region 116.
In addition, array 100 includes a first channel strip 120 that lies between n+ source strip 112 and n− drain extension region 116, and a second channel strip 122 that lies between n+ source strip 114 and n− drain extension region 116. Array 100 also includes a first oxide strip 124 that is formed on first channel strip 120, a second oxide strip 126 that is formed on second channel strip 122, and a field oxide region FOX that is formed in p− semiconductor material 110 and n− drain extension region 116.
As further shown in FIGS. 1A-1B, array 100 includes a first gate 130 that is formed on first oxide strip 124 over first channel strip 120, and a second gate 132 that is formed on second oxide strip 126 over second channel strip 122. In addition, a single line 134 is electrically connected to both of the gates 130 and 132 via contacts 130C and 132C, and a bond pad 136 is electrically connected to single line 134.
In operation, n+ source strip 112, n− drain extension region 116, n+drain strip 118, and gate 130 are the elements of a first MOS device 140, while n+ source strip 114, n− drain extension region 116, n+drain strip 118, and gate 132 are the elements of a second MOS device 142. First MOS device 140 and second MOS device 142 operate in a conventional fashion, and respond to the same voltage on bond pad 136.
When used in a high power application, strong electric fields are present. The strong electric fields accelerate charge carriers in the channel strips into having ionizing collisions with the lattice which, in turn, leads to the formation of hot carriers. Hot carriers, however, degrade a number of device parameters over time.
For example, the series on-resistance and the substrate current degrade (increase) with time as a result of hot carrier damage. Degradation in the series on-resistance and substrate current leads to increased device series resistance and heat dissipation, eventually leading to device failure. The n-channel LDMOS (NLDMOS) transistor is particularly prone to early failure due to increased series on-resistance and substrate current resulting from hot carrier damage.
One condition which can greatly influence the operation of MOS devices 140 and 142 is the misalignment of n− drain extension region 116. As shown in FIG. 1B, n− drain extension region 116 is centered with respect to n+drain region 118. However, process misalignment biases that occur during the manufacturing process can cause n− drain extension region 116 to be shifted either right or left which, in turn, leads to asymmetric device operation.
This asymmetric device operation adversely impacts electrical device parameters, such as breakdown voltage, on-resistance, substrate current and device hot carrier reliability. Thus, there is a need for a method of monitoring these process biases so that they can be eliminated, resulting in LDMOS devices with more symmetrical electrical operation and hot carrier reliability.